DDR protocol refers to a data transfer protocol that allows for data to be fetched on both the rising and falling edges of a clock (referred to as a data strobe or DQS), thus doubling the effective data transfer rate.
According to DDR protocol, data transfer is source-synchronized. That is, a device transmitting data according to the DDR protocol transmits a clock signal along with the data signal, where the data signal is synchronized with the clock signal.
A device receiving the data uses the clock signal to sample the data at the appropriate times. FIG. 1 shows a clock signal 110 and a data signal 120 to be sampled. The portion of data signal 120 shown includes five bits of data, with a first bit 122 equal to a logical zero, second bit 123 equal to a logical one, third bit 124 equal to a logical one, fourth bit 125 equal to a logical zero, and fifth bit 126 equal to a logical zero.
For accurate data sampling, data should be sampled at a time when the data signal not changing. That is, rather than sampling the data signal close to a rising or falling edge (e.g., at a time t1 or a time t2), the data should be sampled at a time during which the signal is not changing (e.g., at a time t3).
FIG. 2 shows a schematic of a system 200 for sampling a data signal between a successive edges of a clock signal, according to the prior art. FIG. 3 shows waveforms that are generated using system 200, as described below.
System 200 includes a clock receiver 210 and a data receiver 220. Clock receiver 210 drives a clock signal 310, while data receiver 220 drives a data signal synchronized with the clock signal.
Clock signal 310 is input to a series of four identical delay elements 230A–230D. A controller 260 controls the amount of the delay so that each of the delay elements 230A–230D delays the signal received at its input by a time equal to one fourth of the time between successive falling edges.
For the symmetric clock signal shown in FIG. 3 (e.g., for T1 equal to T2), the output of delay element 230A is a delayed signal 320, where delayed signal 320 is out of phase with clock signal 310 by 90 degrees. The output of delay element 230B is a delayed signal 330, which is out of phase with clock signal 310 by 180 degrees. The output of delay element 230C is a delayed signal 340, which is out of phase with clock signal 310 by 270 degrees. Finally, the output of delay element 230D is a delayed signal 350, which is in phase with clock signal 310.
In order to adjust the delay of delay elements 230A–230D to be equal to one fourth of the time between successive falling edges, the output of delay element 230D is input to a phase detector 250, as is the un-shifted clock signal. If the delay is correctly adjusted, the output of delay element 230D will be in phase with the un-shifted clock signal (it will have been delayed by exactly one full period of the clock signal). However, if the delay is not correctly adjusted, the output of delay element 230D will be out of phase with the un-shifted clock signal.
Phase detector 250 outputs a signal reflecting any difference in phase between the output of delay element 230D and the un-shifted clock signal. The output of phase detector 250 is provided to a controller 260, which adjusts the delay of delay elements 230A to 230D to reduce the phase difference.
In order to sample the data signal at the appropriate times, delayed signal 320 (i.e., the output of delay element 230A) is provided to a data sampling circuit 225. Data sampling circuit 225 samples data in the data signal on the rising edges of delayed signal 320. For the symmetric clock signal 310 shown in FIG. 3, the rising edges of delayed signal 320 correspond to a mid-point between a rising edge and the successive falling edge of clock signal 310. However, if the duty cycle of clock signal 310 is different than 50% for each half of the signal, the rising edges of delayed signal 320 will be displaced from the mid-point.
Delayed signal 320 is also provided to an inverter 240. For an ideal inverter, the output of inverter 240 is an inverted delayed signal 325. For an ideal inverter and for the symmetric clock signal 310 shown in FIG. 3, the rising edges of inverted delayed signal 325 correspond to the mid-point between a falling edge and a subsequent rising edge of clock signal 310.
However, inverting the output of delay element 230A generally introduces an inverter delay. Thus, the output of a real inverter 240 is an inverted delayed signal 325′. Data sampling circuit 225 samples data in the data signal on the rising edges of inverted delayed signal 325′, which is displaced from the mid-point between the falling edge and subsequent rising edge of clock signal 310 by an amount equal to tdelay.